A compact functional verification flow for a RISC-V 32I based core

Roberto Molina-Robles, Edgar Solera-Bolanos, Ronny Garcia-Ramirez, Alfonso Chacon-Rodriguez, Alfredo Arnaud, Renato Rimolo-Donadio

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.

Original languageEnglish
Title of host publicationPRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131467
DOIs
StatePublished - Feb 2020
Event3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020 - San Jose, Costa Rica
Duration: 25 Feb 202028 Feb 2020

Publication series

NamePRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings

Conference

Conference3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020
Country/TerritoryCosta Rica
CitySan Jose
Period25/02/2028/02/20

Keywords

  • EDA tools
  • Functional Verification
  • RISC-V 32I
  • System Verilog
  • UVM
  • architecture
  • compiler
  • coverage
  • processor
  • reference model
  • regression
  • simulation
  • test generation

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