A compact model for flicker noise in MOS transistors for analog circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.