Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors

Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro

Research output: Contribution to journalArticlepeer-review

98 Scopus citations

Abstract

In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mirrors allow the division of currents with division factors of thousands, without reducing matching or noise performance. SP mirrors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100 nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout techniques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others.

Original languageEnglish
Article number1683892
Pages (from-to)2009-2018
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number9
DOIs
StatePublished - Sep 2006
Externally publishedYes

Keywords

  • Low offset transconductors
  • MOS analog design
  • MOS matching
  • Series-parallel transistors

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