On the design of ultra low noise amplifiers for ENG recording

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Due to the extremely low amplitude of the input signals, the design of electro-neurgo-graph (ENG) amplifiers normally involves special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable devices, because power consumption is restricted to few tens @mW. In this paper, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable electronics are demonstrated. In both cases circuit design and measurement results are presented, showing an excellent performance in circuit simplicity, and noise to power consumption trade-off. The first circuit is a very simple Gm-C chopper low-pass amplifier for flicker noise cancellation. It consumes only 28mW, with a measured input referred noise and offset of 1.2 nV/√Hz , and 2.5μV, respectively. For the reduction of thermal noise with minimum power consumption, in the second circuit, a ultra-low noise amplifier, a energy-efficient DC-DC downconverter, and low voltage design techniques are combined. Measured input referred noise in this case was 5,5 nV/√Hz at only 380iμW power consumption. Both circuits were fabricated in a 1,5 micron technology.

Original languageEnglish
Title of host publicationProceedings - SBCCI 2007
Subtitle of host publication20th Symposium on Integrated Circuits and System Design
PublisherAssociation for Computing Machinery (ACM)
Pages65-70
Number of pages6
ISBN (Print)9781595938169
DOIs
StatePublished - 2007
Externally publishedYes
EventSBCCI 2007: 20th Symposium on Integrated Circuits and System Design - Copacabana, Rio de Janeiro, Brazil
Duration: 3 Sep 20076 Sep 2007

Publication series

NameProceedings - SBCCI 2007: 20th Symposium on Integrated Circuits and System Design

Conference

ConferenceSBCCI 2007: 20th Symposium on Integrated Circuits and System Design
Country/TerritoryBrazil
CityCopacabana, Rio de Janeiro
Period3/09/076/09/07

Keywords

  • Analog design
  • CMOS
  • Low-noise
  • Low-power

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