TY - GEN
T1 - Siwa
T2 - 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
AU - Garcia-Ramirez, R.
AU - Chacon-Rodriguez, A.
AU - Castro-Gonzalez, R.
AU - Arnaud, A.
AU - Miguez, M.
AU - Gak, J.
AU - Molina-Robles, R.
AU - Madrigal-Boza, G.
AU - Oviedo-Hernandez, M.
AU - Solera-Bolanos, E.
AU - Salazar-Sibaja, D.
AU - Sanchez-Jimenez, D.
AU - Fonseca-Rodriguez, M.
AU - Arrieta-Solorzano, J.
AU - Rimolo-Donadio, R.
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - The design of Siwa1, a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.
AB - The design of Siwa1, a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.
KW - Digital VLSI
KW - IMD
KW - Micro-Architecture
KW - RISC-V
KW - System-on-Chip
UR - http://www.scopus.com/inward/record.url?scp=85081697523&partnerID=8YFLogxK
U2 - 10.1109/LASCAS45839.2020.9068952
DO - 10.1109/LASCAS45839.2020.9068952
M3 - Contribución a la conferencia
AN - SCOPUS:85081697523
T3 - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
BT - 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 February 2020 through 28 February 2020
ER -