TY - GEN
T1 - A compact functional verification flow for a RISC-V 32I based core
AU - Molina-Robles, Roberto
AU - Solera-Bolanos, Edgar
AU - Garcia-Ramirez, Ronny
AU - Chacon-Rodriguez, Alfonso
AU - Arnaud, Alfredo
AU - Rimolo-Donadio, Renato
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.
AB - The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.
KW - EDA tools
KW - Functional Verification
KW - RISC-V 32I
KW - System Verilog
KW - UVM
KW - architecture
KW - compiler
KW - coverage
KW - processor
KW - reference model
KW - regression
KW - simulation
KW - test generation
UR - http://www.scopus.com/inward/record.url?scp=85084055452&partnerID=8YFLogxK
U2 - 10.1109/PRIME-LA47693.2020.9062717
DO - 10.1109/PRIME-LA47693.2020.9062717
M3 - Contribución a la conferencia
AN - SCOPUS:85084055452
T3 - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
BT - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020
Y2 - 25 February 2020 through 28 February 2020
ER -