Characterization of MOS transistor current mismatch

H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

9 Citas (Scopus)

Resumen

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, and allows the assessment of mismatch from process and geometric parameters.

Idioma originalInglés
Título de la publicación alojadaProceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004
EditorialAssociation for Computing Machinery (ACM)
Páginas33-38
Número de páginas6
ISBN (versión impresa)1581139470, 9781581139471
DOI
EstadoPublicada - 2004
Publicado de forma externa
EventoProceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004 - Pernambuco
Duración: 7 set. 200411 set. 2004

Serie de la publicación

NombreProceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Conferencia

ConferenciaProceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004
País/TerritorioBrazil
CiudadPernambuco
Período7/09/0411/09/04

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