TY - GEN
T1 - Compact Time-Based Sensor-to-Digital Converters in Skywater 130nm Open-Source Technology
AU - Marin, Jorge
AU - Vourkas, Ioannis
AU - Rojas, Christian A.
AU - Gak, Joel
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents two implementations of a highly-digital time-based sensor-to-digital converter (SDC) targeted for high resolution, low power and ultra-compact circuit footprint. The core structure uses the phase-locked loop (PLL)-based architecture, which leads to a highly linear transfer function that enables a simple calibration scheme. The SDCs have been designed using the Skywater 130nm technology and open-source design tools. In the first implementation, the converter has been applied to a capacitive sensor interface application by including the sensor as a capacitive load in a ring oscillator node. The simulated SDC converts capacitive values in a range between 8pF and 8.3pF. Secondly, a novel resistive SDC for temperature measurements between -40°C and 155°C has been implemented in the same technology. The full-system circuit simulation of the resistive SDC shows a SQNR of 12.9ENOB for a 6.2μs sampling period and a power consumption of 1.7mW, using only 0.008mm2 of silicon area.
AB - This paper presents two implementations of a highly-digital time-based sensor-to-digital converter (SDC) targeted for high resolution, low power and ultra-compact circuit footprint. The core structure uses the phase-locked loop (PLL)-based architecture, which leads to a highly linear transfer function that enables a simple calibration scheme. The SDCs have been designed using the Skywater 130nm technology and open-source design tools. In the first implementation, the converter has been applied to a capacitive sensor interface application by including the sensor as a capacitive load in a ring oscillator node. The simulated SDC converts capacitive values in a range between 8pF and 8.3pF. Secondly, a novel resistive SDC for temperature measurements between -40°C and 155°C has been implemented in the same technology. The full-system circuit simulation of the resistive SDC shows a SQNR of 12.9ENOB for a 6.2μs sampling period and a power consumption of 1.7mW, using only 0.008mm2 of silicon area.
KW - CMOS integrated circuits
KW - open source silicon
KW - sensor interface
UR - http://www.scopus.com/inward/record.url?scp=85159706780&partnerID=8YFLogxK
U2 - 10.1109/LASCAS56464.2023.10108228
DO - 10.1109/LASCAS56464.2023.10108228
M3 - Contribución a la conferencia
AN - SCOPUS:85159706780
T3 - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
BT - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
A2 - Huerta, Monica Karel
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023
Y2 - 27 February 2023 through 3 March 2023
ER -