TY - GEN
T1 - On the design of very small transconductance OTAs with reduced input offset
AU - Arnaud, Alfredo
AU - Florelli, Rafaella
AU - Galup-Montoro, Carlos
PY - 2005
Y1 - 2005
N2 - In this paper it will be demonstrated, from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without degrading mismatch or noise performance. SP current-division will be then employed to design OTAs ranging from a few pS to a few nS, with up to 1V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3s time-constant integrator will also be presented. One-by-one several design non-idealities will be revised: linearity, offset, noise, leakages; as well as layout techniques. A final analysis concludes that SP-association of transistors allows to build very efficient transconductors, for demanding applications in the field of implantable electronics among others.
AB - In this paper it will be demonstrated, from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without degrading mismatch or noise performance. SP current-division will be then employed to design OTAs ranging from a few pS to a few nS, with up to 1V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3s time-constant integrator will also be presented. One-by-one several design non-idealities will be revised: linearity, offset, noise, leakages; as well as layout techniques. A final analysis concludes that SP-association of transistors allows to build very efficient transconductors, for demanding applications in the field of implantable electronics among others.
KW - Analog design
KW - CMOS
KW - Low-power
UR - http://www.scopus.com/inward/record.url?scp=33750928016&partnerID=8YFLogxK
U2 - 10.1109/SBCCI.2005.4286825
DO - 10.1109/SBCCI.2005.4286825
M3 - Contribución a la conferencia
AN - SCOPUS:33750928016
SN - 1595931740
SN - 9781595931740
T3 - SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design
SP - 15
EP - 20
BT - SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design
T2 - SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design
Y2 - 4 September 2005 through 7 September 2005
ER -